(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, relates to a nonvolatile semiconductor memory device for storing information depending upon a polarization state of a ferroelectric material intervening between ferroelectric capacitor electrodes.
(2) Description of the Related Art
As follows is a description of a conventional ferroelectric memory device with reference to FIG. 1.
Memory cells MC arranged in an array have a capacitance C for storing information make use of ferroelectric material (hereinafter referred to as "capacitor C") and a MOS transistor Q, respectively, and are arranged in a matrix so as to form a memory cell array 30 to enable to write, read and erase of the information of the memory cell MC.
With the memory cell array 30, to a word line (WL0, WL1 . . . ) is connected in common a gate terminal of the transistor Q of the memory cell MC in the same column, and to a plate line (PL0, PL1 . . . ) is connected in common one of the electrodes of the capacitor C of the memory cell in the same column, and word lines WL and plate lines PL are alternately arranged one by one.
Moreover, a bit line (BL0, /BL0, BL1, /BL1 . . . ) is connected in common to either the drain or source of the transistor of the memory cell in the same row. Therefore, memory cells are arranged in a matrix as a whole, corresponding to nodes of bit lines BL, /BL, word lines WL and plate lines PL.
In FIG. 1, of a plurality of bit lines arranged in parallel to each other in the row direction, a pair of adjacent bit lines BL and /BL are shown together with a construction in the vicinity thereof. With respect to a bit line BL of the pair of bit lines BL and /BL, the other bit line /BL is also referred to as a "complementary bit line". In the following description (including the drawings), as a symbol showing the complementary bit line, there is used "/BL" or "BL" with an upper line ".sup.-- ", but both of them are used in the same meaning.
One end of the bit line BL and the complementary bit line /BL extending in the row direction of the memory cell MC is connected to a sense amplifier 31 for amplifying and detecting the potential difference between the bit line BL and the complementary bit line /BL.
Moreover, as shown in FIG. 1, the above described each bit line BL, /BL and plate line PL are connected to a bit line potential supply circuit 32 and a plate potential supply circuit 33, respectively, for supplying optional predetermined potential for each line, and a plurality of memory cells MC are connected between the above described adjacent bit line BL and /BL.
Next is a description of a method for writing binary data "1" in a conventional memory cell having the above described memory array construction, taking an example of a method for giving optional certain potential to the plate line PL in FIG. 2A.
The method for writing data "1" is performed in the following manner, as shown in FIG. 2A. That is to say, positive power supply voltage Vcc is supplied to a bit line BL corresponding to a memory cell MC to be written, and at the same time, potential of the ground level is supplied to a complementary bit line /BL. Then a corresponding word line WL is set to "H" level, and MOS transistors Q1 and Q2 included in the memory cell MC to be written are made "ON", that is, drain and source are connected to supply the power supply voltage Vcc to one of the electrodes of a capacitor C1.
Here, optional predetermined potential Vp has been already supplied to a corresponding plate line PL, since the power is switched on, and voltage at a level corresponding to the power supply voltage Vcc is applied to the bit line BL, to thereby generate electric field EVcc1, occurring between the both electrodes of capacitor C1, at a level determined by subtracting the predetermined potential Vp of the plate line PL from Vcc. With this electric field, electric charge corresponding to the polarization Ps1 shown in FIG. 3A is stored in the capacitor C1 to thereby store the polarization state.
On the other hand, since voltage of the ground potential level has been supplied to the complementary bit line /BL, electric field EVcc2 of a level subtracting the ground potential from the optional predetermined potential Vp of the plate line PL is generated between both electrodes of the capacitor C2. With this electric field, polarization Ps2 shown in FIG. 2A is stored in the capacitor C2 to thereby store the polarization information.
When the word line WL is made "OFF", since optional predetermined potential Vp has been supplied to the plate line PL, it is necessary to make the potential of the opposite pole equal. Therefore, it is necessary to periodically refresh the electrode of the capacitor C1 on the side connected to the bit line BL and to periodically refresh the electrode of the capacitor C2 on the side connected to the complementary bit line /BL.
In this case, if it is assumed that both poles of the capacitor have the same potential, the electric field between both poles becomes 0, and polarization Pr1 (FIG. 3A) remains in the capacitor C1, and polarization Pr2 (FIG. 4A) remains in the capacitor C2.
Moreover, when the power supply voltage Vcc is not provided (specifically, when the power supply voltage Vcc is 0V), the potential of both poles of the capacitor is the ground potential level, and polarization Pr is stored.
In the above description, write of data "1" has been explained. Write of data "0" is realized by reversing the voltage level supplied to the bit line BL and the complementary bit line /BL in the case of data "1" described above. That is to say, the ground potential level is supplied to the bit line BL, and the power supply voltage Vcc is supplied to the complementary bit line /BL, thereby residual polarization Pr1 remains in the capacitor C2, contrary to the case of writing the above data "1", and residual polarization Pr2 remains in the capacitor C1. Hence, data "0" is written in the memory cell.
Furthermore, read of the written data is performed as described below.
First, prior to the read operation, as shown in FIG. 2B, the bit line BL and the complementary bit line /BL are discharged to the ground potential level, then subsequently, the potential of the word line WL is made to be "H" level, to thereby make the MOS transistors Q1 and Q2 ON, to start the read operation. At this time, the potential of the plate line PL is always the optional predetermined potential Vp.
Then, in the case of reading data "1", the MOS transistor Q1 is ON, and the voltage of the ground potential level applied to the capacitor C1, to thereby generate the electric field in the opposite direction to that of the write case between the potential Vp of the plate line PL and the capacitor C1. Thereby, the polarization state of the ferroelectric film included therein is inverted, to inverse the storage state of polarization in the capacitor C1.
On the other hand, since the electric field in the same direction as that of the write case is formed in the capacitor C2, polarization of the ferroelectric film included therein is not inverted. Hence, inversion of the storage state of polarization in the capacitor C2 is not caused. However, the storage amount of polarization changes slightly, with application of the electric field.
Then, electric charge in an amount corresponding to the change of the stored polarization in the capacitors C1 and C2 flows into the bit line BL and the complementary bit line /BL. The potential of the bit line BL becomes slightly larger than that of the complementary bit line /BL, due to the difference in an amount of electric charge flowing therein. By amplifying and detecting the potential difference between the bit line BL and the complementary bit line /BL with the sense amplifier 31 in FIG. 1, the stored data "1" is read.
In the case of reading data "0", the electric field in the opposite direction to that of the write case is applied to the capacitor C2, due to the potential difference of the plate line PL, to thereby inverse the polarization of the ferroelectric film included therein, hence the storage state of polarization in the capacitor C2 is inverted.
On the other hand, since the electric field in the same direction as that of the write case is applied to the capacitor C1, polarization of the ferroelectric film included therein is not inverted. However, the storage amount of polarization changes slightly, with application of the electric field.
Then, electric charge in an amount corresponding to the change of the stored polarization in the capacitors C1 and C2 flows into the bit line BL and the complementary bit line /BL, respectively. The potential of the complementary bit line /BL becomes slightly larger than that of the bit line BL, due to the difference in the amount of electric charge flowing therein. By amplifying and detecting the potential difference between the bit line BL and the complementary bit line /BL with the sense amplifier 31 in FIG. 1, the stored data "0" is made readable.
However, as the polarization information, even if, for example, "1" is written, and residual polarization Pr1 remains, when the electric field Evcc1' (EVcc&lt;0) opposite to the state that "1" is written is applied due to some reasons (for example, at the time of power on, when optional predetermined potential is supplied to an optional node connected to the memory cell capacitor), the hysteresis curve becomes smaller (FIG. 3B) than that of FIG. 3A showing the original hysteresis curve. Thereby, at the time of read, the electric charge quantity read by the bit line BL decreases to cause deterioration of the sense margin.
On the contrary, when the value of the above Evcc1' is large, there is a problem that inversion of polarization is caused to thereby write the opposite data (FIG. 3C).
Even in a case that "0" is written in the ferroelectric capacitor C, the above problems are caused, that is, the hysteresis becomes smaller (FIG. 4B) relative to the original hysteresis (FIG. 4A), or erroneous write is caused (FIG. 4C).
To solve the above described problems, heretofore, Japanese Unexamined Patent Publication No. Hei 8-124379 discloses a semiconductor memory device in which a memory cell array 42 is provided with an erroneous write preventing circuit 41 which makes the word line WL and the bit line BL have the same potential only at the time of power on, using a power on reset circuit 40 outlined in FIG. 5.
With the above described semiconductor memory device, the power on reset circuit 40 is so constructed as to generate a power on signal PWRON which becomes "H" level for a certain period of time at the time of power on. With the power on signal PWRON, a bit line potential generation circuit and an SSR circuit (not shown) are controlled to thereby control the occurrence of respective potentials (VBL, VBB and the like), and meaningless access at the time of power on is prevented by controlling stop and release of the operation of an access control circuit (not shown).
Moreover, the erroneous write preventing circuit 41 is for preventing inversion of polarization and failure of memory data in a memory cell in the ferroelectric memory cell MC with the power on signal PWRON generated by the power on reset circuit 40, and transistors Q1 and Q2 for switches are connected between at least all bit lines BL and predetermined potential nodes (Vss in the drawing).
Therefore, by inputting the power on signal PWRON, for example, at "H" level for a certain period of time, at the time of power on, to each gate terminal of switching transistors Q, the same ground potential Vss is applied to all of plate lines PL and bit lines BL via the switching transistors Q1.about.Q2 to thereby prevent such problems as inversion of polarization and failure of memory data in the ferroelectric memory cell MC at the time of power on and at the time of resetting the power.
In the ferroelectric memory adopting the method where optional predetermined potential is applied to plate lines PL or bit lines BL, however, at the time of power on or at the time of returning from the power down mode, the MOS transistor Q becomes OFF (not connect), and external electric field is not applied to the memory retaining node of the ferroelectric capacitor C connected to the MOS transistor Q. Therefore, only polarization exists in the memory retaining node regardless of the state of the nonvolatile data, and its potential is in a floating state. Accordingly, when optional predetermined potential is applied to bit lines BL and plate lines PL, or at the time of power on or at the time of returning from the power down mode, and in the case of the plate line PL potential reaches to a certain level by noise caused carelessly, the potential of the memory retaining node follows the potential of plate line PL and changes because of coupling of the ferroelectric capacitor. Due to the parasitic capacity of the memory retaining node, however, potential difference is caused between both ends of the capacitor C, hence there is a possibility of causing erroneous write.
Furthermore, as shown in FIG. 5, it is necessary to prepare switching transistors Q1 and Q2 for each bit line BL side and plate line PL side, resulting in a problem of increasing the area of the memory cell array.